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Subject: [hwloc-devel] Stability of /sys/devices/system/cpu/cpu0/cache/index*/ interface
From: Jiri Hladky (hladky.jiri_at_[hidden])
Date: 2011-10-04 17:52:31

Hi Brice,
hi everybody,

I'm involved in the project haveged:

which is a (true) random number generator which is using internal states of
CPU like TLB, branching predictor and so on. In order to work properly it
requires the knowledge of L1 data and instruction cache.

The current implementation is using cpuid to find this. It works fine on
Intel and AMD but the trouble is on PPC where cpuid is missing. I have
suggested to use


but the author is concerned with the stability of this kernel
interface. Since hwloc relies also on /sys/devices/system/cpu/cpu0/cache/
I'm wondering if you had some thoughts or issues on that.

Thanks a lot for any input!