I am not an expert, by any means, but based on a presentation I heard 4
The Xeon and Phi instruction sets have a large intersection, but neither is
a subset of the other.
In particular, Phi has its own SIMD instructions *instead* of Xeon's MMX,
There is also on CMPXCHG16B instruction on Phi, among others.
So, there will need to be different binaries, or "fat" binaries that branch
based on CPU type.
On Thu, May 2, 2013 at 5:47 PM, Ralph Castain <rhc_at_[hidden]> wrote:
> On May 2, 2013, at 5:12 PM, Christopher Samuel <samuel_at_[hidden]>
> > -----BEGIN PGP SIGNED MESSAGE-----
> > Hash: SHA1
> > Hi folks,
> > The new system we're bringing up has 10 nodes with dual Xeon Phi MIC
> > cards, are there any plans to support them by launching MPI tasks
> > directly on the Phis themselves (rather than just as offload devices
> > for code on the hosts)?
> We had something similar at one time - I developed it for the Roadrunner
> cluster so you could run MPI tasks on the GPUs. Worked well, but eventually
> fell into disrepair due to lack of use.
> In this case, I suspect it will be much easier to do as the Phis appear to
> be a lot more visible to the host than the GPU did on RR. Looking at the
> documentation, the Phis just sit directly on the PCIe bus, so they should
> look just like any other processor, and they are Xeon binary compatible -
> so there is no issue with tracking which binary to run on which processor.
> Brice: do the Phis appear in the hwloc topology object?
> Chris: can you run lstopo on one of the nodes and send me the output
> > All the best,
> > Chris
> > - --
> > Christopher Samuel Senior Systems Administrator
> > VLSCI - Victorian Life Sciences Computation Initiative
> > Email: samuel_at_[hidden] Phone: +61 (0)3 903 55545
> > http://www.vlsci.org.au/ http://twitter.com/vlsci
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Paul H. Hargrove PHHargrove_at_[hidden]
Future Technologies Group
Computer and Data Sciences Department Tel: +1-510-495-2352
Lawrence Berkeley National Laboratory Fax: +1-510-486-6900