I have a simple question for the shared memory (sm) module developers of
In the current implementation, is there any advantage of having shared
cache among processes communicating?
For example let say we have P1 and P2 placed in the same CPU on 2
different physical cores with shared cache, P1 wants to send a message
to P2 and the message is already in the cache.
How the message is being actually exchanged? Is the cache line
invalidated, written to main memory and exchanged by using some DMA
transfer... or is the message in the cache used (avoiding access to the
thanks in advance, Simone P.