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Subject: Re: [hwloc-devel] Strange results on itanium 2
From: Jirka Hladky (jhladky_at_[hidden])
Date: 2010-10-31 17:38:24


On Sunday, October 31, 2010 09:45:04 am Brice Goglin wrote:
> Le 30/10/2010 00:55, Jirka Hladky a écrit :
> > > >> L2 and one L1 per core. Your machine has hyperthreading, so our
> > > >>
> > > >> This work-around worked fine on old itaniums since they had one
> >
> > L3, one
> >
> > > >> work-around creates one L3 per thread, while L1 and L2 (properly
> > > >>
> > > >> reported by the kernel) are core-specific. Maybe hwloc should just
> > > >>
> > > >> ignore caches with invalid shared_cpu_map.
> >
> > BTW, it's Intel Itanium2 9140N CPU with 18MB of L3 cache.
>
> It looks all Itaniums (even the latest 93xx ones) have per-core L1/L2/L3
> caches. Nothing is ever shared between cores. So a best workaround would
> be to use the core cpuset (both threads) when the cache cpuset is wrong
> (instead of using the thread cpuset like we do right now). I'll likely
> commit that later.
>
> Brice

Thanks Brice!

Jirka