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Subject: [OMPI devel] problem with absent L3 on AMD CPU
From: Andriy Gapon (avg_at_[hidden])
Date: 2011-04-10 03:47:37


It seems that lstopo can get mightly confused with AMD Athlon II processor
(family 10h) that doesn't have L3 cache.

I believe that the following patch should fix that:
--- src/topology-x86.c.orig 2011-04-10 10:38:39.370239628 +0300
+++ src/topology-x86.c 2011-04-10 10:38:44.573256245 +0300
@@ -59,10 +59,6 @@
   unsigned cachenum;
   unsigned size = 0;

- cachenum = infos->numcaches++;
- infos->cache = realloc(infos->cache, infos->numcaches*sizeof(*infos->cache));
- cache = &infos->cache[cachenum];
-
   if (level == 1)
     size = ((cpuid >> 24)) << 10;
   else if (level == 2)
@@ -72,6 +68,10 @@
   if (!size)
     return;

+ cachenum = infos->numcaches++;
+ infos->cache = realloc(infos->cache, infos->numcaches*sizeof(*infos->cache));
+ cache = &infos->cache[cachenum];
+
   cache->type = 1;
   cache->level = level;
   if (level <= 2)

Otherwise, numcaches gets incremented and the cache array grows a new entry, but
that new entry is not initialized. Maybe this is an OS or envrionment specific
problem, but at least here on FreeBSD the new memory is not zero-ed out and
POSIX doesn't require realloc to do that.

This report is for the version 1.1.2.
Apologies for the noise if this problem is already fixed in newer code.

Thanks!

-- 
Andriy Gapon